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| Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES * Repetitive Avalanche Rated * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance PHP2N60E, PHB2N60E, PHD2N60E SYMBOL d QUICK REFERENCE DATA VDSS = 600 V g ID = 1.9 A RDS(ON) 6 s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHP2N60E is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB2N60E is supplied in the SOT404 surface mounting package. The PHD2N60E is supplied in the SOT428 surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain1 source SOT78 (TO220AB) tab SOT404 tab SOT428 tab 2 2 drain 1 23 1 3 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 600 600 30 1.9 1.2 7.6 50 150 UNIT V V V A A A W C 1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages. August 1998 1 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated AVALANCHE ENERGY LIMITING VALUES PHP2N60E, PHB2N60E, PHD2N60E Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy CONDITIONS MIN. MAX. 144 UNIT mJ Unclamped inductive load, IAS = 1 A; tp = 0.32 ms; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig:17 Repetitive avalanche energy2 IAR = 1.9 A; tp = 1 s; Tj prior to avalanche = 25C; RGS = 50 ; VGS = 10 V; refer to fig:18 Repetitive and non-repetitive avalanche current EAR IAS, IAR - 4 1.9 mJ A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 and SOT428 packages, pcb mounted, minimum footprint TYP. MAX. UNIT 60 50 2.5 K/W K/W K/W 2 pulse width and repetition rate limited by Tj max. August 1998 2 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage V(BR)DSS / Drain-source breakdown Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage Forward transconductance gfs IDSS Drain-source leakage current IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss V(BR)DSS CONDITIONS PHP2N60E, PHB2N60E, PHD2N60E MIN. 600 2.0 0.5 - TYP. MAX. UNIT 0.1 4.6 3.0 1.4 1 50 10 20 2 9 10 20 60 20 3.5 4.5 7.5 236 34 20 6 4.0 100 500 200 25 3 15 V %/K V S A A nA nC nC nC ns ns ns ns nH nH nH pF pF pF VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1 A VDS = 600 V; VGS = 0 V VDS = 480 V; VGS = 0 V; Tj = 125 C Gate-source leakage current VGS = 30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 2 A; VDD = 480 V; VGS = 10 V VDD = 300 V; RD = 150 ; RG = 24 Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 2 A; VGS = 0 V IS = 2 A; VGS = 0 V; dI/dt = 100 A/s MIN. TYP. MAX. UNIT 360 2.4 1.9 7.6 1.2 A A V ns C August 1998 3 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHP2N60E, PHB2N60E, PHD2N60E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth j-mb / (K/W) D= 0.5 0.2 0.1 0.05 0.1 0.02 0 T 0.01 t 0.1s 10ms P D tp D= tp T 1 0 20 40 60 80 100 Tmb / C 120 140 10us 1ms t/s Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating 4 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID, Drain current (Amps) Tj = 25 C 10 V 3 6.5 V 6V 2 5.5 V 1 5V VGS = 4.5 V PHP1N60A 20 V 120 110 100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 Tmb / C 100 120 140 0 0 5 10 15 20 VDS, Drain-Source voltage (Volts) 25 30 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V PHP1N60 tp = 10 us 100us 1 ms Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS Drain-Source on resistance, RDS(ON) (Ohms) 5V 5.5 V 10 Drain current, ID (Amps) Tmb = 25 C RD 1 N S(O )= VD D S/I 12 10 PHP1N60A Tj = 25 C 6V 8 6 4 2 6.5 V 10 V VGS = 20 V DC 0.1 10 ms 100ms 0.01 10 100 Drain-source voltage, VDS (Volts) 1000 0 0 1 2 3 Drain current, ID (Amps) 4 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS August 1998 4 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHP2N60E, PHB2N60E, PHD2N60E 5 Drain current, ID (A) VDS > ID x RDS(on)max PHP1N60A 4 VGS(TO) / V max. 4 3 typ. 3 min. 2 2 150 C 1 Tj = 25 C 0 0 1 0 2 4 6 Gate-source voltage, VGS (V) 8 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj Transconductance, gfs (S) VDS > ID x RDS(on)max PHP1N60A Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 2 1E-01 1E-02 1.5 Tj = 25 C 1 150 C 1E-04 1E-03 2% typ 98 % 0.5 1E-05 0 1E-06 0 1 2 3 Drain current, ID (A) 4 5 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Capacitances, Ciss, Coss, Crss (pF) PHP1N60A 1000 Ciss 2 100 Coss 1 10 Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 1 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 1 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz August 1998 5 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHP2N60E, PHB2N60E, PHD2N60E 20 Gate-Source voltage, VGS (Volts) ID = 2 A 240 V 120 V PHP1N60A 10 Source-drain diode current, IF(A) VGS = 0 V PHP1N60A 15 VDD = 480 V 8 150 C 6 Tj = 25 C 10 4 5 2 0 0 10 20 Gate charge, Qg (nC) 30 40 0 0 0.5 1 Source-Drain voltage, VSDS (V) 1.5 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times, td(on), tr, td(off), tf (ns) VDD = 300 V RD = 150 Ohms Tj = 25 C PHP1N60A Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj 1000 Non-repetitive Avalanche current, IAS (A) 10 100 td(off) 1 Tj prior to avalanche = 25 C 10 tr tf td(on) VDS tp ID 125 C PHP2N60E 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 1 0.1 1E-06 0 20 40 60 Gate resistance, RG (Ohms) 80 100 Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load 1.15 1.1 1.05 Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C Maximum Repetitive Avalanche Current, IAR (A) 10 1 1 Tj prior to avalanche = 25 C 125 C 0.95 0.9 0.85 -100 0.1 PHP2N60E 0.01 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) August 1998 6 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 2 g PHP2N60E, PHB2N60E, PHD2N60E 4,5 max 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 2,54 2,54 0,9 max (3x) 0,6 2,4 Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". August 1998 7 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g 10.3 max PHP2N60E, PHB2N60E, PHD2N60E 4.5 max 1.4 max 11 max 15.4 2.5 0.85 max (x2) 2.54 (x2) 0.5 Fig.20. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.21. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". August 1998 8 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA PHP2N60E, PHB2N60E, PHD2N60E Dimensions in mm : Net Mass: 1.4 g seating plane 6.73 max 1.1 2.38 max 0.93 max 5.4 tab 4 min 6.22 max 10.4 max 4.6 2 1 3 0.5 min 0.3 0.5 0.5 0.8 max (x2) 2.285 (x2) Fig.22. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 2.5 1.5 4.57 Fig.23. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". August 1998 9 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHP2N60E, PHB2N60E, PHD2N60E This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1998 10 Rev 1.100 |
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